David H. Boyle

 

SUMMARY OF QUALIFICATIONS 

 

Senior level engineer with 30 years of experience in all aspects of ASIC design, with the following skills:

 

• 14 ASIC / 11 FPGA Designs 

• ATM Networking

• Verilog, Synopsys, Synplicity 

• UNIX, PC Platforms 

• C Programming 

 

SECURITY CLEARANCE 

 

TSSI, with CI polygraph 

 

 

CHRONOLOGICAL WORK EXPERIENCE 

May 2006 – present: PTR Group 

• FPGA and board design for a digital RF modem 

 

September 1998 – May 2006:  Senior Principal Engineer, SPARTA, Inc.  

• For the VBULite and VBU Ultra programs, designed the FPGA to handle the transmission of a serial stream across the PCI bus.  

• Designed a PC board glue chip that includes the IDE, PIC, Timer, RTC, USB, and PCI functions.  

• Designed a cardbus modem.  

• Designed a HDSL to E1 line interface card.  Designed a USB 1.1 interface device.  

• Designed an IP core 8051 microcontroller.  

• Designed an IP core PCI controller.  

• Designed a 10/100 Ethernet interface card.  

• Designed a cardbus based hard drive backup system.  

• Designed a HDLC add/drop multiplexor.  

• Designed a cardbus size single board computer with Au1500 processor and a serial ATA controller.  

• Designed a compact flash controller. 

                                                                                                                                                                                     

May 1996 – August 1998:  Principal Engineer, Hyundai Network Systems

• Line Interface Module:  Took a minimal set of requirements and developed an architectural approach to satisfy them.  Wrote a white paper detailing this approach.

• Designed a 750K gate ASIC, which is a 16x16 port ATM switch fabric.  Runs at 100 MHz, handles OC-12 traffic, expandable to do OC-24 and OC-48; total capacity of 40 Gbits.  Tested and synthesized the part.

• Debugged a 10 Gig ATM switch fabric board and Line Interface Module.  The board contains seven FPGAs as well as 12 switch fabric ASICs.  

• Designed an OC-12 / quad OC-3 line interface ASIC.  The 80K gate part handles reception of cell data from the fabric interface, translating the header back to ATM, and transmitting the cell on the output fiber through a UTOPIA interface.  

• Lead designer of the four port switch fabric ASIC.  This part is 300K gates, runs at 80 MHz, and allows for multilayer OC-12 switching.  Successful on the first pass of silicon.

January 1994 – May 1996:  Senior Engineer, Pulsecom

Lead designer for a quad DS1 ASIC that took four T1 data streams in and byte interleaved them into a VT superframe.  The part also did T1 framing and HDLC data link extraction.  The part was 75K gates, and ran at 7 MHz, with a 52 MHz synthetic clock generator.

 

July 1994 - December 1994:  Contract Employee, E-Systems

Worked on a Segmentation and Reassembly ASIC for an ATM Network Interface Adapter.  Responsibilities included test generation and several sections of the design including AAL5 translation and SONET interfaces.

 

August 1979 –  April 1994:  Staff Engineer, IBM Federal Systems

• Developed high speed clock amplifier and high voltage off chip driver for the Power PC processor.  

• Part of design team that developed the IBM PRIZMA ATM switch element; a 16x16 OC-12 capable ASIC with 350K gates and runs at 66 MHz.  Met all requirements on first pass.  

• Designed a system to convert analog signals into discrete frequency components.  

• Designed analog interface, FFT interface, and board with driver to deliver data to PC for display.  

• Developed (circuit design, layout, modeling and test) a radiation hardened test chip which was a technology demonstration vehicle for the GVSC contract.  

• Designed video memory controller for the PS/2 model 25/30.  

• Developed CMOS ASIC libraries for standard cell products.  

• Lead designer of an 8051 macro core, including chip design, test bench development, hardware verification design, and chip modeling using a high level language.  

• Designed library modules for IBM standard cell ASIC libraries, including circuit design, modeling, and verification of manufactured parts. 

 

May 1976 – August 1979:  Engineer, Westinghouse Electric Corporation

Developed analog and digital ASIC designs for satellite and radar applications. 

 

SPECIAL ACHIEVEMENTS 

 

• Four patents for circuit designs 

• 13 technical publications for circuit designs and software algorithms 

• Award for finding and fixing a problem on an ASIC product 

 

EDUCATION 

BSEE, Carnegie Mellon University, Pittsburgh, PA, 1976 

 

TRAINING 

 

Data Communications, Northern Virginia Community College, 1995 

C Programming, Northern Virginia Community College, 1994 

Pascal Programming, Northern Virginia Community College, 1981